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ds07-12507-2e fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l mb89810a series mb89816a/p817a n description the mb89810a series is a line of single-chip microcontrollers based on the f 2 mc*-8l cpu core which can operate at low voltage but at high speed. the microcontrollers contain peripheral function such as timer, serial interface, a uart, and an external interrupt. the mb89810a series is applicable to a wide range of applications from welfare products to industrial equipment, including portable devices. *: f 2 mc stands for fujitsu flexible microcontroller. n features high speed processing at low voltage minimum execution time: 0.8 m s/3.0 v, 1.33 m s/2.2 v ?f 2 mc-8l family cpu core ? four types of timers 8-bit pwm timer: 2 channels (also serve as reload timers) 16-bit timer/counter 21-bit time-base timer ? two serial interface 8-bit synchronous serial (switchable transfer direction allows communication with various equipment.) uart (5-, 7-, or 8-bit transfer capable) (continued) n pac k ag e multiplication and division instructions 16-bit arithmetic operations test and branch instructions bit manipulation instructions, etc. instruction set optimized for controllers (fpt-64p-m06) 64-pin plastic qfp
2 mb89810a series (continued) ? external interrupt: 8 channels eight channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). ? low-power consumption modes stop mode (oscillation stops to minimize the current consumption) sleep mode (the cpu stops to reduce the current consumption to approx. 1/3 of normal) n product lineup (continued) MB89P817A classification mass-production product (mask rom products) one-time prom product (for evaluation and development) rom size 24 k 8 bits (internal mask rom) 32 k 8 bits (internal prom, programming with gen- eral-purpose eprom programmer) ram size 2048 8 bits cpu functions number of instructions: 136 instruction bit length: 8 bits instruction length: 1 to 3 bytes data bit length: 1, 8, 16 bits minimum execution time: 0.8 m s/5 mhz interrupt processing time: 7.2 m s/5 mhz ports input ports: 8 (all also serve as peripherals.) output ports: 8 i/o ports (n-ch open-drain): 5 (for led driving) i/o ports (cmos): 32 (14 ports also serve as peripherals.) total: 53 8-bit pwm timer two internal channels 8-bit reload timer operation (toggled output capable, operating clock cycle: 3 different cycles) 8-bit resolution pwm operation (conversion cycle: 3 different cycles) 8-bit timer/counter 16-bit timer operation 16-bit event counter operation uart 5-, 7-, or 8-bit transfer capable built-in baud rate generator clock synchronous/asynchronous data transfer capable 8-bit serial i/o 8-bits lsb-first/msb first selectability one clock selectable from four transfer clocks (one external shift clock, three internal shift clocks) external interrupt 8 independent channels (edge selection, interrupt vector, source flag) 4 channels: level detection (level selectable) 4 channels: edge detection (edge selectable) used also for wake-up from the stop/sleep mode. (edge detection is also permitted in stop mode.) mb89816a part number parameter
3 mb89810a series (continued) * : varies with conditions such as the operating frequency. (see section n electrical characteristics.) n pin assignment MB89P817A watch interrupt interrupt cycles: 4 different cycles (subclock) watchdog timer reset reset occurrence cycle: 839 ms/5 mhz standby mode sleep mode, stop mode process cmos package fpt-64p-m06 operating voltage 2.2 v to 6.0 v* 2.7 v to 6.0 v* mb89816a (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 p30/pwe p31/sck p32/so p33/si p34/pwo p35/pwi p36/pto1 p37/pto2 p60/int0 p61/int1 p62/int2 v cc p63/int3 p64/int4 p65/int5 p66/int6 p67/int7 x0a x1a 20 21 22 23 24 25 26 27 28 29 30 31 32 rst mod0 mod1 x0 x1 v ss p27 p26 p25 p24 p23 p22 p21 64 63 62 61 60 59 58 57 56 55 54 53 52 p47/scl2 p46/rxd2 p45/txd2 p44/scl1 p43/rxd1 p42/txd1 p41/ec v cc p40 p54 p53 p52 p51 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p50 v ss p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 p20 (fpt-64p-m06) part number parameter
4 mb89810a series n pin description (continued) pin no. pin name circuit type function 23 x0 a main clock oscillator pins 24 x1 18 x0a i subclock crystal oscillator pins 19 x1a 21 mod0 b operating mode selection pins connect directly these pins directly to v ss . 22 mod1 20 rst c reset i/o pin this pin is an n-ch open-drain output type with a pull-up resistor and a hysteresis input type. l is output from this pin by an internal reset source. the internal circuit is initialized by the input of l. 49 to 42 p00 to p07 d general-purpose i/o ports a pull-up resistor option is provided. these ports have the port output inverting function. 41 to 34 p10 to p17 d general-purpose i/o ports a pull-up resistor option is provided. these ports have the port output inverting function. 33 to 30 p20 to p23 f general-purpose output ports these ports have the port output inverting function. 29 to 26 p24 to p27 f general-purpose output ports 1 p30 /pwe e general-purpose i/o port a pull-up resistor option is provided. also serves as a pulse width detection enable input (pwe). pwe input is hysteresis input. 2p31/sck e general-purpose i/o port a pull-up resistor option is provided. also serves as the clock i/o for the 8-bit serial i/o (sck). sck input is hysteresis input. 3 p32/so d general-purpose i/o port a pull-up resistor option is provided. also serves as the data output for the 8-bit serial i/o (so). 4 p33/si e general-purpose i/o port a pull-up resistor option is provided. also serves as the data input for the 8-bit serial i/o (si). si input is hysteresis input. 5 p34/pwo d general-purpose i/o port a pull-up resistor option is provided. also serves as a pulse width detection output (pwo). 6 p35/pwi e general-purpose i/o port a pull-up resistor option is provided. also serves as a pulse width detection input (pwi). pwi input is hysteresis input. 7 p36/pto1 d general-purpose i/o port a pull-up resistor option is provided. also serves as the toggle output for the 8-bit pwm timer 1 (pto1).
5 mb89810a series (continued) pin no. pin name circuit type function 8 p37/pto2 d general-purpose i/o port a pull-up resistor option is provided. also serves as the toggle output for the 8-bit pwm timer 2 (pto2). 56 p40 d general-purpose i/o port a pull-up resistor option is provided. 58 p41/ec e general-purpose i/o port a pull-up resistor option is provided. also serves as a 16-bit timer/counter input (ec). ec input is hysteresis input. 59 p42/txd1 d general-purpose i/o port a pull-up resistor option is provided. also serves as the data output 1 for the uart (txd1). 60 p43/rxd1 e general-purpose i/o port a pull-up resistor option is provided. also serves as the data input 1 for the uart (rxd1). rxd1 input is hysteresis input. 61 p44/scl1 e general-purpose i/o port a pull-up resistor option is provided. also serves as the clock i/o 1 for the uart (scl1). scl1 input is hysteresis input. 62 p45/txd2 d general-purpose i/o port a pull-up resistor option is provided. also serves as the data output 2 for the uart (txd2). 63 p46/rxd2 e general-purpose i/o port a pull-up resistor option is provided. also serves as the data input 2 for the uart (rxd2). rxd2 input is hysteresis input. 64 p47/scl2 e general-purpose i/o port a pull-up resistor option is provided. also serves as the clock i/o 2 for the uart (scl2). scl2 input is hysteresis input. 51 to 55 p50 to p54 g n-channel open-drain i/o ports a pull-up resistor option is provided only for the mb89816a. 9 to 11 p60/int0 to p62/int2 h general-purpose i/o ports a pull-up resistor option is provided. also serve as an external interrupt input (int0 to int2). these ports are a hysteresis input type. 13 to 17 p63/int3 to p67/int7 h general-purpose i/o ports a pull-up resistor option is provided. also serve as an external interrupt input (int3 to int7). these ports are a hysteresis input type. 12, 57 v cc C power supply pin 25, 50 v ss C power supply (gnd) pin
6 mb89810a series n i/o circuit type (continued) type circuit remarks a ? main clock ? at an oscillation feedback resistor of approximately 2 m w (1 to 5 mhz) ? cr oscillator circuit selectability b c ? at an output pull-up resistor (p-ch) of approximately 50 k w /5.0 v ? hysteresis input d ? cmos output ? cmos input ? pull-up resistor optional e ? cmos output ? cmos input ? hysteresis input (resource input) ? pull-up resistor optional x1 x0 standby control signal p-ch n-ch r p-ch r n-ch p-ch p-ch r n-ch p-ch
7 mb89810a series (continued) type circuit remarks f ? cmos output g ? n-ch open-drain output ? cmos input ? pull-up resistor optional (only for the mb89816a) h ? hysteresis input ? pull-up resistor optional i ? subclock (30 to 40 khz) ? at an oscillation feedback resistor of approximately 4.5 m w p-ch n-ch r n-ch p-ch x1a x0a
8 mb89810a series n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on 1. absolute maximum ratings in section n electrical characteristics is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency (50 to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched. 4. precautions when using an external clock even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode.
9 mb89810a series n programming to the eprom on the MB89P817A in eprom mode, the MB89P817A functions equivalent to the mbm27c256a. this allows the prom to be programmed with a general-purpose eprom programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. ? writing procedure (1) set the eprom programmer to the mbm27c256a. (2) load program data into the eprom programmer at 0007 h to 7fff h (note that addresses 8007 h to ffff h while operating as operating mode assign to 0007 h to 7fff h in eprom mode). load option data into addresses 0000 h to 0006 h of the eprom programmer. (for information about each corresponding option, see setting otprom option bit map.) (3) program with the eprom programmer. ? memory space memory space is diagrammed below. 7fff h 0000 h 0007 h program area (prom) option area
10 mb89810a series ? recommended screening conditions high-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked otprom (one-time prom) microcomputer program. ? programming yield all bits cannot be programmed at fujitsu shipping test to a blanked otprom microcomputer, due to its nature. for this reason, a programming yield of 100% cannot be assured at all times. ? eprom programmer socket adapter inquiry: sun hayato co., ltd.: tel 81-3-3802-5760 note: connect the jumper pin to v ss when using. depending on the eprom programmer, inserting a capacitor of approx. 0.1 m f between v pp and v ss or v cc and v ss can stabilize programming operations. package compatible socket adapter fpt-64p-m06 rom-64qf-28dp-8l program, verify aging +150?, 48 hrs. data verification assembly
11 mb89810a series ? otprom option bit map note: each bit defaults to 1. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0000 h vacancy readable and writable vacancy readable and writable vacancy readable and writable single-clock setting 1: dual-clock 0: single-clock reset pin output 1: enabled 0: disabled power-on reset 1: enabled 0: disabled oscillation stabilization time 00 2 4 /f ch 10 2 17 /f ch 01 2 14 /f ch 11 2 18 /f ch 0001 h p07 pull-up 1: no 0: yes p06 pull-up 1: no 0: yes p05 pull-up 1: no 0: yes p04 pull-up 1: no 0: yes p03 pull-up 1: no 0: yes p02 pull-up 1: no 0: yes p01 pull-up 1: no 0: yes p00 pull-up 1: no 0: yes 0002 h p17 pull-up 1: no 0: yes p16 pull-up 1: no 0: yes p15 pull-up 1: no 0: yes p14 pull-up 1: no 0: yes p13 pull-up 1: no 0: yes p12 pull-up 1: no 0: yes p11 pull-up 1: no 0: yes p10 pull-up 1: no 0: yes 0003 h p37 pull-up 1: no 0: yes p36 pull-up 1: no 0: yes p35 pull-up 1: no 0: yes p34 pull-up 1: no 0: yes p33 pull-up 1: no 0: yes p32 pull-up 1: no 0: yes p31 pull-up 1: no 0: yes p30 pull-up 1: no 0: yes 0004 h p47 pull-up 1: no 0: yes p46 pull-up 1: no 0: yes p45 pull-up 1: no 0: yes p44 pull-up 1: no 0: yes p43 pull-up 1: no 0: yes p42 pull-up 1: no 0: yes p41 pull-up 1: no 0: yes p40 pull-up 1: no 0: yes 0005 h vacancy readable and writable vacancy readable and writable vacancy readable and writable p64 pull-up 1: no 0: yes p63 pull-up 1: no 0: yes p62 pull-up 1: no 0: yes p61 pull-up 1: no 0: yes p60 pull-up 1: no 0: yes 0006 h vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writables oscillator type 1: crystal 0: cr p67 pull-up 1: no 0: yes p66 pull-up 1: no 0: yes p65 pull-up 1: no 0: yes
12 mb89810a series n block diagram 8 8-bit serial i/o 1 8-bit pwm timer 1 8-bit pwm timer 2 time-base timer p37/pto2 pulse width detection cmos i/o port p36/pto1 p31/sck p33/si p32/so p30/pwe p35/pwi p34/pwo uart 16-bit timer/counter cmos i/o port p44/scl1 p41/ec p47/scl2 p43/rxd1 p46/rxd2 p42/txd1 p45/txd2 p40 external interrupt input port p60/int0 to p67/int7 port 5 n-ch open-drain i/o port main clock oscillator subclock oscillator reset circuit (wdt) port 0 and port 1 cmos i/o port 8 port 2 cmos output port 8 ram (2048 8 bits) 8 8 5 p50 to p54 x0 x1 x0a x1a rst p00 to p07 p10 to p17 p20 to p27 v cc 2, v ss 2 mod0, mod1 clock controlletr internal bus port 3 port 4 port 6 f 2 mc-8l cpu rom (24 k 8 bits) other pins
13 mb89810a series n cpu core 1. memory space the microcontrollers of the mb89810a series offer a memory space of 64 kbytes for storing all of i/o, data, and program areas. the i/o area is located at the lowest address. the data area is provided immediately above the i/o area. the data area can be divided into register, stack, and direct areas according to the application. the program area is located at exactly the opposite end, that is, near the highest address. provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. the memory space of the mb89810a series is structured as illustrated below. memory space 0000 h 0080 h 0100 h 0880 h register 0200 h i/o ram 2 kb mb89816a not available a000 h ffff h rom 24 kb 0000 h 0080 h 0100 h 0880 h register 0200 h i/o ram 2 kb MB89P817A not available 8000 h ffff h prom 32 kb 8007 h optional prom
14 mb89810a series 2. registers the f 2 mc-8l family has two types of registers; dedicated registers in the cpu and general-purpose registers in the memory. the following dedicated registers are provided: program counter (pc): a 16-bit register for indicating instruction storage positions accumulator (a): a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t): a 16-bit register which performs arithmetic operations with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix): a 16-bit register for index modification extra pointer (ep): a 16-bit pointer for indicating a memory address stack pointer (sp): a 16-bit register for indicating a stack area program status (ps): a 16-bit register for storing a register pointer, a condition code the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code register (ccr). (see the diagram below.) pc a t ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h undefined undefined undefined undefined undefined i-flag = 0, il1, 0 = 11 other bits are undefined. initial value structure of the program status register vacancy h i il1, 0 n z vc 54 rp ps 109876 3210 15 14 13 12 11 rp ccr vacancy vacancy
15 mb89810a series the rp indicates the address of the register bank currently in use. the relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of cpu operations at the time of an interrupt. h-flag: set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. cleared otherwise. this flag is for decimal adjustment instructions. i-flag: interrupt is allowed when this flag is set to 1. interrupt is prohibited when the flag is set to 0. set to 0 when reset. il1, 0: indicates the level of the interrupt currently allowed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-flag: set if the msb is set to 1 as the result of an arithmetic operation. cleared when the bit is set to 0. z-flag: set when an arithmetic operation results in 0. cleared otherwise. v-flag: set if the complement on 2 overflows as a result of an arithmetic operation. reset if the overflow does not occur. c-flag: set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared otherwise. set to the shift-out value in the case of a shift instruction. il1 il0 interrupt level high-low 00 1 high low = no interrupt 01 10 2 11 3 rule for conversion of actual addresses of the general-purpose register area ? a15 ? a14 ? a13 ? a12 ? a11 ? a10 ? a9 ? a8 r4 a7 r3 a6 r2 a5 r1 a4 r0 a3 b2 a2 b1 a1 b0 a0 rp generated addresses lower op codes
16 mb89810a series the following general-purpose registers are provided: general-purpose registers: an 8-bit register for storing data the general-purpose registers are 8 bits and located in the register banks of the memory. one bank contains eight registers and up to a total of 32 banks can be used on the mb89816a. the bank currently in use is indicated by the register bank pointer (rp). register bank configuration this address = 0100 h + 8 (rp) memory area 32 banks r 0 r 1 r 2 r 3 r 4 r 5 r 6 r 7
17 mb89810a series n i/o map (continued) address read/write register name register description 00 h (r/w) pdr0 port 0 data register 01 h (w) ddr0 port 0 data direction register 02 h (r/w) pdr1 port 1 data register 03 h (w) ddr1 port 1 data direction register 04 h (r/w) pdr2 port 2 data register 05 h vacancy 06 h vacancy 07 h (r/w) sycc system clock control register 08 h (r/w) stbc standby control register 09 h (r/w) wdtc watchdog timer control register 0a h (r/w) tbcr time-base timer control register 0b h (r/w) wpcr watch prescaler control register 0c h (r/w) pdr3 port 3 data register 0d h (w) ddr3 port 3 data direction register 0e h (r/w) pdr4 port 4 data register 0f h (w) ddr4 port 4 data direction register 10 h (r/w) pdr5 port 5 data register 11 h (r) pdr6 port 6 data register 12 h vacancy 13 h vacancy 14 h vacancy 15 h vacancy 16 h vacancy 17 h (r/w) pive port inverting operation enable register 18 h (r/w) tmcr 16-bit timer count register 19 h (r/w) tchr 16-bit timer count register (h) 1a h (r/w) tclr 16-bit timer count register (l) 1b h vacancy 1c h (r/w) smr serial i/o mode register 1d h (r/w) sdr serial i/o data register 1e h vacancy 1f h vacancy
18 mb89810a series (continued) note: do not use vacancies. address read/write register name register description 20 h (r/w) smc1 uart serial i/o mode control register 1 21 h (r/w) src uart serial i/o rate control register 22 h (r/w) ssd uart serial i/o status/data control register 23 h (r/w) sidr/sodr uart serial i/o data control register 24 h (r/w) smc2 uart serial i/o mode control register 2 25 h vacancy 26 h vacancy 27 h vacancy 28 h (r/w) cntr1 pwm timer control register 1 29 h (r/w) cntr2 pwm timer control register 2 2a h (r/w) cntr3 pwm timer control register 3 2b h (w) comr2 pwm timer compare register 2 2c h (w) comr1 pwm timer compare register 1 2d h vacancy 2e h vacancy 2f h (r/w) pwcr pulse width detection control register 30 h (r/w) eic1 external interrupt 1 control register 1 31 h (r/w) eic2 external interrupt 1 control register 2 32 h (r/w) ei2e external interrupt 2 enable register 33 h (r/w) ei2f external interrupt 2 flag register 34 h vacancy 35 h to 7a h vacancy 7b h vacancy 7c h (w) ilr1 interrupt level register 1 7d h (w) ilr2 interrupt level register 2 7e h (w) ilr3 interrupt level register 3 7f h not available itr interrupt test register
19 mb89810a series n electrical characteristics 1. absolute maximum ratings (v ss = 0.0 v) precautions: permanent device damage may occur if the above absolute maximum ratings are exceeded. func- tional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol value unit remarks min. max. power supply voltage v cc v ss C 0.3 v ss + 7.0 v input voltage v i1 v ss C 0.3 v cc + 0.3 v except p50 to p54 v i2 v ss C 0.3 v ss + 7.0 v p50 to p54 output voltage v o1 v ss C 0.3 v cc + 0.3 v except p50 to p54 v o2 v ss C 0.3 v ss + 7.0 v p50 to p54 l level maximum output current i ol 20 ma peak value l level average output current i olav1 4ma average value except pins other than p50 to p54 i olav2 10 ma average value for p50 to p54 l level total maximum output current ? i ol 100 ma peak value l level total average output current ? i olav 40 ma average value h level maximum output current i oh C20 ma peak value h level average output current i ohav C4 ma average value h level total maximum output current ? i oh C50 ma peak value h level total average output current ? i ohav C20 ma average value power consumption p d 300mw operating temperature t a C40 +85 c storage temperature tstg C55 +150 c
20 mb89810a series 2. recommended operating conditions (v ss = 0.0 v) * : these values vary with the operating frequency. see figure 1. figure 1 operating voltage vs. main clock operating frequency (for mb89816a) parameter symbol value unit remarks min. max. power supply voltage v cc 2.2* 6.0 v normal operation assurance range mb89816a 2.7* 6.0 v normal operation assurance range MB89P817A 1.5 6.0 v retains the ram state in stop mode h level voltage v ih 0.7 v cc v cc + 0.3 v p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p54 (with pull-up resistor) v ihs 0.8 v cc v cc + 0.3 v rst , mod0, mod1, p60 to p67, pheripheral input for port 3 and port 4 v ihs2 0.8 v cc v ss + 6.0 v p50 to p54 (without pull-up resistor) l level voltage v il v ss C 0.3 0.3 v cc v p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p54 v ils v ss C 0.3 0.2 v cc v rst , mod0, mod1, p60 to p67, pheripheral input for port 3 and port4 open-drain output pin application voltage v d v ss C 0.3 v ss + 6.0 v p50 to p54 (without pull-up resistor) operating temperature t a C40 +85 c 1 2 3 4 5 6 1.0 5.0 operating assurance range operating voltage (v) 3.0 4.0 2.0 main clock operating frequency (mhz) (at an instruction cycle of 4/f ch ) note: the shaded area is assured only for the mb89816a
21 mb89810a series 3. dc characteristics (v cc = +5.0 v, v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter symbol pin condition value unit remarks min. typ. max. h level output voltage v oh p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47 i oh = C2.0 ma 2.4 v l level output voltage v ol1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p54 p60 to p67 i ol = 1.8 ma 0.4 v v ol2 p50 to p54 i ol = 6 ma v cc = 3 v 0.5v v ol3 rst i ol = 4.0 ma 0.4 v input leakage current (hi-z output leakage current) i li1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p54, p60 to p67, mod0, mod1 0.45 v < v i < v cc 5 m a without pull-up resistor pull-up resistance r pull p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p54, p60 to p67, rst v i = 0.0 v 25 50 100 k w with pull-up resistor power supply current * i cc1 v cc f ch = 5 mhz v cc = 5.0 v t inst = 0.8 m s 4 6 ma mb89816a 4.8 7.5 ma MB89P817A i cc2 f ch = 5 mhz v cc = 3.0 v t inst = 6.4 m s 0.4 0.6 ma mb89816a 1.0 1.5 ma MB89P817A i ccs1 f ch = 5 mhz v cc = 5.0 v t inst = 0.8 m s 1.2 1.8 ma sleep mode i ccs2 f ch = 5 mhz v cc = 3.0 v t inst = 12.8 m s 0.3 0.5 ma i ccl f cl = 32.768 khz v cc = 3.0 v 50 100 m a subclock mode 500 700 m a MB89P817A
22 mb89810a series (continued) (v cc = +5.0 v, v ss = 0.0 v, t a = C40 c to +85 c) * : the measurement conditions of power supply current are as follows: the external clock and t a = +25 c. parameter symbol pin condition value unit remarks min. typ. max. power supply current * i ccls v cc f cl = 32.768 khz v cc = 3.0 v 1550 m a subclock sleep mode i cct f cl = 32.768 khz v cc = 3.0 v 15 m a watch mode main clock stop mode at dual- clock system i cch f cl = 32.768 khz v cc = 3.0 v 10 m a subclock stop mode main clock stop mode at single-clock system input capacitance c in other than v cc and v ss f = 1 mhz 10 pf
23 mb89810a series 4. ac characteristics (1) reset timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: t ch is the cycle time of the main clock. (2) power-on reset (av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: make sure that power supply rises within the selected oscillation stabilization time. if power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. parameter symbol condition value unit remarks min. max. rst l pulse width t zlzh 16 t ch ns parameter symbol condition value unit remarks min. max. power supply rising time t r 50 ms power-on reset function only power supply cut-off time t off 1 ms due to repeated operations 0.2 v cc 0.2 v cc rst t zlzh note that a sudden increase in supply voltage may result in a power-on reset. when increasing the supply voltage during operation, voltage variation should be within twice the intended increment so that th e voltage rises as smoothly as possible . 0.2 v 0.2 v 2.0 v 0.2 v t r v cc t off
24 mb89810a series (3) clock timing (av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin condition value unit remarks min. typ. max. clock frequency f ch x0, x1 1 5mhz f cl x0a, x1a 32.768 khz clock cycle time t ch x0, x1 200 1000 ns t cl x0a, x1a 30.5 m s input clock pulse width p wh p wl x0 20 ns external clock p whl p wll x0a 15.2 m s input clock rising/falling time t cr t cf x0 10 ns external clock 0.2 v cc x0 0.2 v cc x0 x1 t ch when a crystal or ceramic resonator is used x0 x1 when an external clock is used open 0.2 v cc 0.8 v cc 0.8 v cc t cr t cf x0 x1 when a cr oscillator is used p wh p wl x0 and x1 timing and conditions main clock conditions
25 mb89810a series (4) serial i/o timings (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : t inst represents the minimum instruction execution time. it varies with the selected system clock and operating mode. parameter symbol pin condition value unit remarks min. max. serial clock cycle time t scyc1 sck internal shift clock mode 2 t inst ns sck ? so time t slov1 sck , so C200 200 ns valid si ? sck - t ivsh1 si, sck 1/2 t inst ns sck - ? valid si hold time t shix1 sck , si 1/2 t inst ns serial clock h pulse width t shsl sck external shift clock mode 1 t inst ns serial clock l pulse width t slsh 1 t inst ns sck ? so time t slov2 sck , so 0 200 ns valid si ? sck - t ivsh2 si, sck 1/2 t inst ns sck - ? valid si hold time t shix2 sck , si 1/2 t inst ns 0.2 v cc x0a 0.2 v cc x0a x1a t cl when a crystal or ceramic resonator is used x0a x1a when an external clock is used open 0.2 v cc 0.8 v cc 0.8 v cc t cr t cf p whl p wll x0a and x1a timings and conditions subclock conditions
26 mb89810a series (5) uart timings (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) notes: t inst represents the minimum instruction execution time. it varies with the selected system clock and operating mode. the edge polarity for the slcx input is assumed when lsel bit = 0 for smc2. the polarity is inverted when lsel = 1. parameter symbol pin condition value unit remarks min. max. serial clock cycle time t scyc scl1, scl2 internal shift clock mode 2 t inst ns scl ? txdx time t slov1 sclx, txdx C200 200 ns valid rxdx ? sclx - t ivsh1 rxdx, sclx 1/2 t inst ns sclx - ? valid rxdx hold time t shix1 scl1, rxd2 1/2 t inst ns serial clock h pulse width t shsl scl1, scl2 external shift clock mode 1 t inst ns serial clock l pulse width t slsh 1 t inst ns sclx ? txdx time t slov2 sclx, txdx 0 200 ns valid rxdx ? sclx - t ivsh2 rxdx, sclx 1/2 t inst ns sclx - ? valid rxdx hold time t shix2 scl1, rxd2 1/2 t inst ns t scyc t slov1 t shix1 t ivsh1 sck/sclx 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc so/txdx si/rxdx t slsh t slov2 t shix2 t ivsh2 sck/sclx 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc so/txdx si/rxdx 0.2 v cc t shsl 0.8 v cc internal shift clock mode external shift clock mode
27 mb89810a series (6) peripheral input timings (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) notes: t inst represents the minimum instruction execution time. it varies with the selected system clock and operating mode. t cl represents the subclock cycle time. the pwe pulse width value varies with the first divider selection bit of the watch prescaler. the pulse width is 512 t cl + 200 when divide by 16 is selected; or "480 t cl + 200" when divide by 15 is selected. parameter symbol pin condition value unit remarks min. max. peripheral input h pulse width t ilih ec, int0 to int7 2 t inst ns peripheral input l pulse width t ihil ec, int0 to int7 2 t inst ns h input pulse width of pulse width detection enable signal t pweh pwe 512 t cl + 200 or 480 t cl + 200 ns l input pulse width of pulse width detection enable signal t pwel 512 t cl + 200 or 480 t cl + 200 ns 0.2 v cc 0.8 v cc t ihil ec, int0 to int7 0.2 v cc t ilih pwe 0.8 v cc 0.2 v cc 0.8 v cc t pweh 0.2 v cc t pwel 0.8 v cc
28 mb89810a series n instructions execution instructions can be divided into the following four groups: ? transfer ? arithmetic operation ? branch ? others table 1 lists symbols used for notation of instructions. table 1 instruction symbols (continued) symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir: b bit direct address (8:3 bits) rel branch relative address (8 bits) @ register indirect (example: @a, @ix, @ep) a accumulator a (whether its length is 8 or 16 bits is determined by the instruction in use.) ah upper 8 bits of accumulator a (8 bits) al lower 8 bits of accumulator a (8 bits) t temporary accumulator t (whether its length is 8 or 16 bits is determined by the instruction in use.) th upper 8 bits of temporary accumulator t (8 bits) tl lower 8 bits of temporary accumulator t (8 bits) ix index register ix (16 bits)
29 mb89810a series (continued) columns indicate the following: mnemonic: assembler notation of an instruction ~: number of instructions #: number of bytes operation: operation of an instruction tl, th, ah: a content change when each of the tl, th, and ah instructions is executed. symbols in the column indicate the following: ? C indicates no change. ? dh is the 8 upper bits of operation description data. ? al and ah must become the contents of al and ah immediately before the instruction is executed. ? 00 becomes 00. n, z, v, c: an instruction of which the corresponding flag will change. if + is written in this column, the relevant instruction will change its corresponding flag. op code: code of an instruction. if an instruction is more than one code, it is written according to the following rule: example: 48 to 4f ? this indicates 48, 49, ... 4f. symbol meaning ep extra pointer ep (16 bits) pc program counter pc (16 bits) sp stack pointer sp (16 bits) ps program status ps (16 bits) dr accumulator a or index register ix (16 bits) ccr condition code register ccr (8 bits) rp register bank pointer rp (5 bits) ri general-purpose register ri (8 bits, i = 0 to 7) indicates that the very is the immediate data. (whether its length is 8 or 16 bits is determined by the instruction in use.) ( ) indicates that the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) (( )) the address indicated by the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.)
30 mb89810a series table 2 transfer instructions (48 instructions) notes: during byte transfer to a, t ? a is restricted to low bytes. operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (reverse arrangement of f 2 mc-8 family) mnemonic ~ # operation tl th ah n z v c op code mov dir,a mov @ix +off,a mov ext,a mov @ep,a mov ri,a mov a,#d8 mov a,dir mov a,@ix +off mov a,ext mov a,@a mov a,@ep mov a,ri mov dir,#d8 mov @ix +off,#d8 mov @ep,#d8 mov ri,#d8 movw dir,a movw @ix +off,a movw ext,a movw @ep,a movw ep,a movw a,#d16 movw a,dir movw a,@ix +off movw a,ext movw a,@a movw a,@ep movw a,ep movw ep,#d16 movw ix,a movw a,ix movw sp,a movw a,sp mov @a,t movw @a,t movw ix,#d16 movw a,ps movw ps,a movw sp,#d16 swap setb dir: b clrb dir: b xch a,t xchw a,t xchw a,ep xchw a,ix xchw a,sp movw a,pc 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ? (a) ( (ix) +off ) ? (a) (ext) ? (a) ( (ep) ) ? (a) (ri) ? (a) (a) ? d8 (a) ? (dir) (a) ? ( (ix) +off) (a) ? (ext) (a) ? ( (a) ) (a) ? ( (ep) ) (a) ? (ri) (dir) ? d8 ( (ix) +off ) ? d8 ( (ep) ) ? d8 (ri) ? d8 (dir) ? (ah),(dir + 1) ? (al) ( (ix) +off) ? (ah), ( (ix) +off + 1) ? (al) (ext) ? (ah), (ext + 1) ? (al) ( (ep) ) ? (ah),( (ep) + 1) ? (al) (ep) ? (a) (a) ? d16 (ah) ? (dir), (al) ? (dir + 1) (ah) ? ( (ix) +off), (al) ? ( (ix) +off + 1) (ah) ? (ext), (al) ? (ext + 1) (ah) ? ( (a) ), (al) ? ( (a) ) + 1) (ah) ? ( (ep) ), (al) ? ( (ep) + 1) (a) ? (ep) (ep) ? d16 (ix) ? (a) (a) ? (ix) (sp) ? (a) (a) ? (sp) ( (a) ) ? (t) ( (a) ) ? (th),( (a) + 1) ? (tl) (ix) ? d16 (a) ? (ps) (ps) ? (a) (sp) ? d16 (ah) ? (al) (dir): b ? 1 (dir): b ? 0 (al) ? (tl) (a) ? (t) (a) ? (ep) (a) ? (ix) (a) ? (sp) (a) ? (pc) C C C C C al al al al al al al C C C C C C C C C al al al al al al C C C C C C C C C C C C C C C al al C C C C C C C C C C C C C C C C C C C C C C C C C ah ah ah ah ah ah C C C C C C C C C C C C C C C C ah C C C C C C C C C C C C C C C C C C C C C C C C C dh dh dh dh dh dh dh C C dh C dh C C C dh C C al C C C dh dh dh dh dh C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 45 46 61 47 48 to 4f 04 05 06 60 92 07 08 to 0f 85 86 87 88 to 8f d5 d6 d4 d7 e3 e4 c5 c6 c4 93 c7 f3 e7 e2 f2 e1 f1 82 83 e6 70 71 e5 10 a8 to af a0 to a7 42 43 f7 f6 f5 f0
31 mb89810a series table 3 arithmetic operation instructions (62 instructions) (continued) mnemonic ~ # operation tl th ah n z v c op code addc a,ri addc a,#d8 addc a,dir addc a,@ix +off addc a,@ep addcw a addc a subc a,ri subc a,#d8 subc a,dir subc a,@ix +off subc a,@ep subcw a subc a inc ri incw ep incw ix incw a dec ri decw ep decw ix decw a mulu a divu a andw a orw a xorw a cmp a cmpw a rorc a rolc a cmp a,#d8 cmp a,dir cmp a,@ep cmp a,@ix +off cmp a,ri daa das xor a xor a,#d8 xor a,dir xor a,@ep xor a,@ix +off xor a,ri and a and a,#d8 and a,dir 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 (a) ? (a) + (ri) + c (a) ? (a) + d8 + c (a) ? (a) + (dir) + c (a) ? (a) + ( (ix) +off) + c (a) ? (a) + ( (ep) ) + c (a) ? (a) + (t) + c (al) ? (al) + (tl) + c (a) ? (a) - (ri) - c (a) ? (a) - d8 - c (a) ? (a) - (dir) - c (a) ? (a) - ( (ix) +off) - c (a) ? (a) - ( (ep) ) - c (a) ? (t) - (a) - c (al) ? (tl) - (al) - c (ri) ? (ri) + 1 (ep) ? (ep) + 1 (ix) ? (ix) + 1 (a) ? (a) + 1 (ri) ? (ri) - 1 (ep) ? (ep) - 1 (ix) ? (ix) - 1 (a) ? (a) - 1 (a) ? (al) (tl) (a) ? (t) / (al),mod ? (t) (a) ? (a) (t) (a) ? (a) (t) (a) ? (a) " (t) (tl) - (al) (t) - (a) (a) - d8 (a) - (dir) (a) - ( (ep) ) (a) - ( (ix) +off) (a) - (ri) decimal adjust for addition decimal adjust for subtraction (a) ? (al) " (tl) (a) ? (al) " d8 (a) ? (al) " (dir) (a) ? (al) " ( (ep) ) (a) ? (al) " ( (ix) +off) (a) ? (al) " (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) C C C C C C C C C C C C C C C C C C C C C C C dl C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 00 C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C dh C C C C dh C C C dh dh 00 dh dh dh C C C C C C C C C C C C C C C C C C C C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + C C C C C C C C C + + C C + + + C C C C C C C C C + + C C C C C C C C C C + + r C + + r C + + r C + + + + + + + + + + C + + + C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C 28 to 2f 24 25 26 27 23 22 38 to 3f 34 35 36 37 33 32 c8 to cf c3 c2 c0 d8 to df d3 d2 d0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1f 84 94 52 54 55 57 56 58 to 5f 62 64 65 a c ? ? ?? a c
32 mb89810a series (continued) table 4 branch instructions (17 instructions) table 5 other instructions (9 instructions) mnemonic ~ # operation tl th ah n z v c op code and a,@ep and a,@ix +off and a,ri or a or a,#d8 or a,dir or a,@ep or a,@ix +off or a,ri cmp dir,#d8 cmp @ep,#d8 cmp @ix +off,#d8 cmp ri,#d8 incw sp decw sp 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (dir) C d8 ( (ep) ) C d8 ( (ix) + off) C d8 (ri) C d8 (sp) ? (sp) + 1 (sp) ? (sp) C 1 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + + + + + + + + + + + + + + + C C C C C C C C 67 66 68 to 6f 72 74 75 77 76 78 to 7f 95 97 96 98 to 9f c1 d1 mnemonic ~ # operation tl th ah n z v c op code bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel blt rel bge rel bbc dir: b,rel bbs dir: b,rel jmp @a jmp ext callv #vct call ext xchw a,pc ret reti 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 if z = 1 then pc ? pc + rel if z = 0 then pc ? pc + rel if c = 1 then pc ? pc + rel if c = 0 then pc ? pc + rel if n = 1 then pc ? pc + rel if n = 0 then pc ? pc + rel if v " n = 1 then pc ? pc + rel if v " n = 0 then pc ? pc + rei if (dir: b) = 0 then pc ? pc + rel if (dir: b) = 1 then pc ? pc + rel (pc) ? (a) (pc) ? ext vector call subroutine call (pc) ? (a),(a) ? (pc) + 1 return from subrountine return form interrupt C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + C C C + C C C C C C C C C C C C C C C C C C C C C C C C C C restore fd fc f9 f8 fb fa ff fe b0 to b7 b8 to bf e0 21 e8 to ef 31 f4 20 30 mnemonic ~ # operation tl th ah n z v c op code pushw a popw a pushw ix popw ix nop clrc setc clri seti 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r C C C s C C C C C C C C 40 50 41 51 00 81 91 80 90
33 mb89810a series n instruction map 0123456789abcdef 0 nop swap ret reti pushw a popw a mov a,ext movw a,ps clri seti clrb dir: 0 bbc dir: 0,rel incw a decw a jmp @a movw a,pc 1 mulu a divu a jmp addr16 call addr16 pushw ix popw ix mov ext,a movw ps,a clrc setc clrb dir: 1 bbc dir: 1,rel incw sp decw sp movw sp,a movw a,sp 2 rolc a cmp a addc a subc a xch a, t xor a and a or a mov @a,t mov a,@a clrb dir: 2 bbc dir: 2,rel incw ix decw ix movw ix,a movw a,ix 3 rorc a cmpw a addcw a subcw a xchw a, t xorw a andw a orw a movw @a,t movw a,@a clrb dir: 3 bbc dir: 3,rel incw ep decw ep movw ep,a movw a,ep 4 mov a,#d8 cmp a,#d8 addc a,#d8 subc a,#d8 xor a,#d8 and a,#d8 or a,#d8 daa das clrb dir: 4 bbc dir: 4,rel movw a,ext movw ext,a movw a,#d16 xchw a,pc 5 mov a,dir cmp a,dir addc a,dir subc a,dir mov dir,a xor a,dir and a,dir or a,dir mov dir,#d8 cmp dir,#d8 clrb dir: 5 bbc dir: 5,rel movw a,dir movw dir,a movw sp,#d16 xchw a,sp 6 mov a,@ix +d cmp a,@ix +d addc a,@ix +d subc a,@ix +d mov @ix +d,a xor a,@ix +d and a,@ix +d or a,@ix +d mov @ix +d,#d8 cmp @ix +d,#d8 clrb dir: 6 bbc dir: 6,rel movw a,@ix +d movw @ix +d,a movw ix,#d16 xchw a,ix 7 mov a,@ep cmp a,@ep addc a,@ep subc a,@ep mov @ep,a xor a,@ep and a,@ep or a,@ep mov @ep,#d8 cmp @ep,#d8 clrb dir: 7 bbc dir: 7,rel movw a,@ep movw @ep,a movw ep,#d16 xchw a,ep 8 mov a,r0 cmp a,r0 addc a,r0 subc a,r0 mov r0,a xor a,r0 and a,r0 or a,r0 mov r0,#d8 cmp r0,#d8 setb dir: 0 bbs dir: 0,rel inc r0 dec r0 callv #0 bnc rel 9 mov a,r1 cmp a,r1 addc a,r1 subc a,r1 mov r1,a xor a,r1 and a,r1 or a,r1 mov r1,#d8 cmp r1,#d8 setb dir: 1 bbs dir: 1,rel inc r1 dec r1 callv #1 bc rel a mov a,r2 cmp a,r2 addc a,r2 subc a,r2 mov r2,a xor a,r2 and a,r2 or a,r2 mov r2,#d8 cmp r2,#d8 setb dir: 2 bbs dir: 2,rel inc r2 dec r2 callv #2 bp rel b mov a,r3 cmp a,r3 addc a,r3 subc a,r3 mov r3,a xor a,r3 and a,r3 or a,r3 mov r3,#d8 cmp r3,#d8 setb dir: 3 bbs dir: 3,rel inc r3 dec r3 callv #3 bn rel c mov a,r4 cmp a,r4 addc a,r4 subc a,r4 mov r4,a xor a,r4 and a,r4 or a,r4 mov r4,#d8 cmp r4,#d8 setb dir: 4 bbs dir: 4,rel inc r4 dec r4 callv #4 bnz rel d mov a,r5 cmp a,r5 addc a,r5 subc a,r5 mov r5,a xor a,r5 and a,r5 or a,r5 mov r5,#d8 cmp r5,#d8 setb dir: 5 bbs dir: 5,rel inc r5 dec r5 callv #5 bz rel e mov a,r6 cmp a,r6 addc a,r6 subc a,r6 mov r6,a xor a,r6 and a,r6 or a,r6 mov r6,#d8 cmp r6,#d8 setb dir: 6 bbs dir: 6,rel inc r6 dec r6 callv #6 bge rel f mov a,r7 cmp a,r7 addc a,r7 subc a,r7 mov r7,a xor a,r7 and a,r7 or a,r7 mov r7,#d8 cmp r7,#d8 setb dir: 7 bbs dir: 7,rel inc r7 dec r7 callv #7 blt rel l h
34 mb89810a series n mask options f ch : main clock frequency * : the main clock oscillation setting time is generated by dividing the main clock frequency. note that the oscillation cycle is not stable immediately after oscillation is started. the settling time value in this data sheet should be used as a reference. n ordering information no. part number mb89816a MB89P817A specifying procedure specify when ordering masking set with eprom programmer 1 pull-up resistors p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p54, p60 to p67 specify by pin can be set per pin. (p50 to p54 are available only for without a pull-up resistor.) 2 power-on reset selection with power-on reset without power-on reset selectable setting possible 3 main clock oscillation (5 mhz) stabilization time selection approx. 218/f ch (approx. 52.4 ms) approx. 217/f ch (approx. 26.2 ms) approx. 214/f ch (approx. 3.2 ms) approx. 24/f ch (approx. 0 ms) selectable setting possible 4 reset pin ouotput selection with reset output without reset output selectable setting possible 5 selection either single- or dual- clock system single clock dual clock selectable setting possible 6 main clock oscillator type selection crystal or ceramic oscillator cr selectable setting possible part number package remarks mb89816apf MB89P817Apf 64-pin plastic qfp (fpt-64p-m06)
35 mb89810a series n package dimensions "a" lead no. 64 52 32 0.25(.010) 0.30(.012) 51 33 1 19 20 index typ (.016.004) 0.400.10 1.00(.0394) 0.150.05(.006.002) 18.00(.709)ref 22.300.40(.878.016) (stand off) 0.05(.002)min 3.35(.132)max (.551.008) 14.000.20 (.642.016) 16.300.40 ref 12.00(.472) (.736.016) 18.700.40 20.000.20(.787.008) 24.700.40(.972.016) (.047.008) details of "b" part 1.200.20 0 10 details of "a" part 0.18(.007)max 0.63(.025)max 0.10(.004) "b" m 0.20(.008) 1994 fujitsu limited f64013s-3c-2 c dimensions in mm (inches) 64-pin plastic qfp (fpt-64p-m06)
36 mb89810a series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 1015, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211, japan tel: (044) 754-3753 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia pacific fujitsu microelectronics asia pte. limited no. 51 bras basah road, plaza by the park, #06-04 to #06-07 singapore 189554 tel: 336-1600 fax: 336-1609 f9606 ? fujitsu limited printed in japan all rights reserved. circuit diagrams utilizing fujitsu products are included as a means of illustrating typical semiconductor applications. com- plete information sufficient for construction purposes is not nec- essarily given. the information contained in this document has been carefully checked and is believed to be reliable. however, fujitsu as- sumes no responsibility for inaccuracies. the information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by fujitsu. fujitsu reserves the right to change products or specifications without notice. no part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of fujitsu. the information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear con- trol systems or medical equipments for life support.

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